\section{TSV RC model in low frequency and DC region}\label{sec:level1}
For circuit performance (delay, power consumption, heat dissipation) estimation, RLC model is the most straight forward modeling method by viewing the device compose of resistance, capacitance and inductance. This section exhibits the papers that modeling TSV as RLC model which is suitable at DC and low frequencies. 

The geometry of TSV influences the final modeling accuracy. Most papers treat TSV as equivalent cylindrical structure\cite{Savidis2009, Khalil2008, Weerasekera2009, Xu2009}. The assumption of extracting TSV structure into a simple cylindrical structure is examined by paper \cite{Savidis2009}. The researchers compared the electrical parameters extracted from a cylinder structure contains both top and bottom copper landing to the proposed simple structure without landing by using Ansoft electromagnetic simulation tool. The results show that only less than a 7\% difference in RLC value, indicating that using simple cylindrical structure is sufficient for accurate TSV modeling. However, this paper only tested results with frequency as high as 1GHz under certain temperature. The conclusion may not be applicable for higher frequency beyond this point.

\subsection{Previous works on simple TSV RLC model}
Most of previous works are on developing simple analytical model for TSV delay simulation. In paper \cite{Khalil2008}, a physical dimension dependent analytical model for the propagation delay of TSVs is proposed. A lumped element model using dimensional analysis method is proposed considering TSVs have a MOS-like capacitor structure \cite{Salah2011}. Similarly, a lumped TSV model and TSV propagation delay analysis is conducted in paper \cite{Katti2010}. The process method will influence the TSV electrical characteristic. An electrical and reliability study based on a fabricated via last TSV is presented in paper \cite{Majeed2010}. As it is illustrated in last section, the structural and material parameters have impact on 3D TSV electrical characteristic. A 3D full wave and spice type circuit simulation is performed and eye-diagrams at different frequencies are used to study this impact \cite{Pak2007}. 

The RLC model for single TSV and coupled TSVs with closed-form expressions are given for various analysis and design purposes\cite{Katti2010, Cho2011, Savidis2009, Weerasekera2009}. In \cite{Cho2011}, a guard ring structure is proposed to suppress the noise coupling in TSVs. Closed-form expressions derived in \cite{Savidis2009} are consist with the empirical expressions in \cite{Weerasekera2009}. And in paper \cite{Weerasekera2009}, in addition to isolated TSV, the coupling effect between TSVs are also considered, which is more practical for full chip circuit simulation. We will take this paper as the main source for TSV RLC modeling at DC and low frequency region.  

\subsection{RLC model for an isolated TSV}
For an isolated TSV, the RLC model is shown in figure \ref{fig:RLC}(a). Capacitances exist between TSV and the adjacent substrate while resistance and inductance are in serial along the TSV. 

\begin{figure}
\includegraphics[width=0.45\textwidth]{figures/RLC1.pdf}
\caption{The resistance, inductance, and capacitance components for (a) an isolated TSV; (b) two coupled TSVs; (c) a TSV bundle}\cite{Weerasekera2009}\label{fig:RLC}
\end{figure}

The resistance can be described as a function of TSV conductivity ($\sigma$), TSV length ($l$), and radius ($r$):
 \begin{equation}
 R_{tsv} = \frac{l_v}{\sigma \pi r_v^2}
 \end{equation}
 
The effective capacitance in TSV is the depletion capacitance and the oxide capacitance acting in serial. The final effective capacitance is a function of its geometry and the effective permittivity ($\epsilon_0$) of surrounding dielectric liner. The expression is based on empirical formula which assumes the thickness of dielectric layer is smaller than $1\mu m$:
 \begin{equation}
 C_{tsv} = \frac{63.36\varepsilon_0 l_v}{ln\left( 1+5.26\frac{l_v}{r_v}\right)}
 \end{equation}
 
When the TSV is treated as a lossy transmission line in the model, the inductance has great impact on signal propagation delay. The propagation delay study in \cite{Khalil2008} shows that without the presence of inductance in TSVs, the average error is 55.2\% higher than RLC model with the value of the distributed RLC. The inductance of an isolated TSV is depended on the geometry parameters. It can be expressed as follows:
 \begin{equation}
 L_{tsv}=\frac{\mu l_v} {2\pi} ln\left(1+\frac{2.84}{\pi}\frac{l_v}{r_v}\right)
 \end{equation}
 
 All the above empirical closed-form equations predict the RLC values within maximum 6\% error verified by a 3D/2D quasi-static electromagnetic-field solver tool. By using these closed-form expressions, the resistance, capacitance, and inductance values in a single TSV can be easily calculated for fast circuit simulation.
 
\subsection{RLC model for coupled TSVs}
 The RLC models for two coupled TSV and a TSV bundle are shown in figure \ref{fig:RLC}(b) and (c), respectively. For coupled TSVs, the resistance expression is the same as the R in an isolated TSV since coupling effect won't influence the resistance. But for inductance and capacitance, the inter-via coupling should be considered. Capacitance and inductance are divided into two parts: self parameter and mutual parameter. 
 
 The capacitance terms of the whole coupled bundle TSV can be expressed as follows:
 \begin{equation}
 C_{bundle}= \begin{bmatrix}
C_{1,1} & -C_{1,2} & ... & -C_{1,n} \\ 
-C_{2,1} & C_{2,2} & ... & -C_{2,n}\\ 
\vdots  & \vdots & \ddots  & \vdots\\ 
-C_{n,1} & -C_{n,2} & ... & C_{n,n}
\end{bmatrix}
 \end{equation}
 
 The diagonal element means the sum of self and inter-via coupling capacitances. This capacitance matrix is sparse because only the diagonal elements and elements that represent nearest neighbors contain meaningful values. From their experiments, for a 7 x 7 TSV bundle, coupling terms for nearest neighbors are much significant than those that are non-adjacent. 
 
 The self capacitance formula is different from the isolated TSV, which is given as:
 \begin{eqnarray}
 C_s &=& C_{tsv}-k_1C_{tsv}e^{(k_2\frac{p_v}{r_v}+k_3\frac{p_v}{l_v})} \nonumber \\
  & &\left[k_4\left(\frac{L_v}{r_v}\right)^{k_5}+k_6\left(\frac{p_v}{r_v}\right )^{k_7}  +k_8\right ]
 \end{eqnarray}
 where $C_{tsv}$ is the capacitance of an isolated TSV, the parameters from $k_1$ to $k_8$ are empirical constants. However, these constants are based on the simulation results and varied with different TSV configurations, making it hard to be directly used in circuit simulation. When $k_2$ and $k_3$ are negative and $p_v$ approaches infinity, $C_s$ equals to $C_{tsv}$.
 
 The formula for the coupling capacitance where $i\neq j$ in the matrix is given as follows:
 \begin{eqnarray}
 & &C_{coupled} = \frac{k_1\epsilon_0l_v}{ln(k_2\frac{pv}{rv})} \nonumber \\
 & & \left[1+k_5\left(\frac{L_v}{r_v}\right)^{k_6}+k_3\left(\frac{p_v}{r_v}\right )^{k_4}  +k_7\left(\frac{p_v}{l_v}\right)^{k_8}\right ]
 \end{eqnarray}
 
 The accuracy of this model is within maximum 6\% error from the simulation results. The coupling inductance terms can also be defined by the matrix similar to the coupling capacitance. Different from capacitance, inductive coupling is long range so the matrix is not sparse. The mutual inductance between any two TSVs can be captured with the following formula:
 \begin{equation}
 L_m=0.199\mu l_vln\left(1+0.438\frac{d_v}{l_v}\right)
 \end{equation}
 where $d_v$ is the center-to-center distance between two TSVs. The maximum error for coupling inductance is within 8\%.
 
 \subsection{RLC model results}
 The RLC values are closely related to the geometry parameters of TSV. First, when the diameter of TSV is fixed, the resistance, inductance and capacitance grow with increased aspect ratio at DC, 1GHz and 2GHz frequencies. Under the same aspect ratio conditions, the resistance increases when the TSV diameter decreased while both the self and coupled capacitance/inductance increase with larger TSV diameter.
 %why inductance increase when TSV size is increased?
As technology scales, the trend for TSV size is smaller diameter and high aspect ratio. Smaller TSV diameter can efficiently reduce the chip footprint while it rises the problem of higher resistance, which will affect the RC delay on TSVs. 
%the depletion capacitance change corresponding to the diameter change?
